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e-Science 2008 4th IEEE International Conference on e-Science

Workshops & Special Sessions

Advances in High-Performance E-Science Middleware and Applications

Analysis of Cache Performance for Processing XML-based Application Data on Multi-core Processors

Presenter and Authors
  • Rajdeep Bhowmik
  • Madhusudhan Govindaraju

Computer architecture is now at an important juncture as single-core CPU power is expected to be nearly constant. The microprocessor industry is rapidly moving towards chip multi-processors (CMPs), commonly referred to as multi-core processors. The transition of CPUs from single to multi-core implementations requires a corresponding shift in the programming paradigm for grid and e-science libraries. Naive implementations of processing on multi-core systems can severely impact performance because of limitations of shared bus bandwidth, cache size and coherency, and communication between threads. To optimize the performance of e-science services, careful application of thread-level parallelism is needed. We study this problem in the context of processing XML data used in grid and e-science applications. The web services model, which strongly leverages XML, has been adopted as the basic architecture for grid and e-science services. As a result, the optimization of separate Web services applications is critical because Web services that are deployed in a longer chain of service processing events must guarantee minimal response times to ensure overall system performance. Our goal is to analyze and provide insightful feedback on cache behavior of each core and reveal performance limitations, bottlenecks, and multi-threaded optimization opportunities for processing XML data relevant to grid and e-science application data formats. We use a micro-architectural emulation framework, Multi-core Grid (McGrid), to generate performance data at various levels of granularity. We analyze cache behavior to quantify the exact gains and present recommendations for processing XML data in grid and e-science applications that will be deployed on emerging multi-core systems.

Date and Time

Thursday, December 11, 1:30–2 p.m.

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